A Hybrid Memory Architecture for Low Power Embedded System Design

On-chip memories are one of the most power hungry components of today’s system on a chips (SoCs). The on-chip memories generally use higher supply (Vdd) and threshold (Vth) voltages than those of logic parts to suppress the static power consumption without increasing the access delay of the memories. This design policy, however, increases the dynamic power consumption since the dynamic power consumption is quadratically proportional to the Vdd. This paper proposes a hybrid memory architecture which consists of the following two regions; 1) a frequently accessed region which uses low Vdd and Vth and 2) a rarely accessed region which uses high Vdd and Vth. The key of our architecture is that the access delays for the two regions are equal to each other, which eases to integrate this memory into processors without major modifications of an internal processor architecture. This paper also proposes a technique for finding the sizes and the code allocation for the regions so as to minimize the total power consumption of the memory. Experimental results demonstrate that the total power consumption of the scratchpad memory can be reduced in every cases.